The invention relates to a semiconductor processing method, and more particularly to an improved trench structure and method for processing a trench such as used as a storage capacitor of a dynamic random access memory.
The semiconductor industry's relentless drive to increase the circuit density of integrated circuits (“ICs” or “chips”) demands that individual devices and circuit elements of a chip be reduced in size. In some dynamic random access memories (DRAMs), trench storage capacitors are used to store data bits. In those DRAMs which contain storage capacitors, the surface area of the chip occupied by the storage capacitor must be reduced with each new generation.
However, achieving such reduction in surface area is not straightforward. The different components of a trench storage capacitor scale unevenly. Some components such as the isolation collar formed in the trench above the storage capacitor cannot be reduced below a certain thickness such as 30 nm.
Trench capacitors are advantageously used in DRAMs because they allow capacitance to be increased without enlarging the surface area occupied by the memory cell. A trench capacitor is formed by etching a vertical structure into the silicon substrate. An increase in the capacitance can be achieved simply by etching a deeper trench, as opposed to “stacked” capacitors that require an increase in the area of the capacitor that occupies the main transistor-bearing surface of the chip. In addition, where planarity of a substrate is desired in processing a chip, trench capacitors are advantageous because their use does not affect the planarity of features on or above the substrate.
FIG. 1 is a cross-sectional view illustrating a prior art trench capacitor structure 10. The trench capacitor structure 10 is formed by a series of steps starting with etching a deep trench 111 into a single crystal region semiconductor substrate 100. The trench 111 includes a bottom 114 and sidewalls 116 and is separated into a lower portion 118 and an upper portion 119. The trench capacitor structure 10 is formed in the lower portion 118, while an isolation collar 160 is formed in the upper portion 119 to provide electrical isolation from nearby devices, such as transistors and other trench capacitors of the chip (not shown).
A buried plate 130 is typically formed in the single-crystal substrate 100 in the lower portion 118 of the trench as the first electrode of the trench capacitor 10. The buried plate 130 is typically formed by out-diffusion of n+ dopants from a dopant source inside the trench 111 into a region of the substrate 100 which surrounds the lower portion 118. For example, an n+ doped glass, such as arsenic-doped silicate glass (ASG), can serve as the dopant source if deposited onto the sidewalls 116 and bottom 114 of the lower portion 118. This would be done after the isolation collar 160 is in place in the upper portion 119. The dopant source is then driven into the lower portion 118 by an annealing process at high temperature. Alternatively, gas phase doping (GPD) could be used, also after the isolation collar 160 is in place.
A capacitor dielectric layer 140 is then formed on the sidewalls of the trench 111. Thereafter, a conductive fill 120, such as n+ doped polycrystalline silicon (herein after “polysilicon” or “poly”) is deposited to fill the lower portion 118 of the trench 111 as a second capacitor electrode.
A buried well region is shown at 170. The buried well 170 serves to provide a connection between buried plates 130 of respective trench storage capacitor of a DRAM array in which the DRAM cell is located.
In some prior art methods, the trench 111 is etched into the semiconductor substrate with the aid of a pad stack 180 which includes a pad oxide layer 182 over which a pad nitride layer 184, also known as a pad stop layer is provided. The pad nitride layer 184 can be superposed with a hard mask layer 190, typically including a layer of deposited oxide.
In some other prior art methods, the final isolation collar is formed prior to subsequent processing steps which form the trench capacitor. The presence of some kind of collar in the upper part of a deep trench is imperative both for forming the buried plate and for the enhancement of node capacitance. The collar acts as a hardmask to block the outdiffusion of a dopant into the sidewalls of the upper part of the trench. The collar also prevents the silicon in the upper part of the trench from being etched.
However, as ever narrower trenches are required to reduce the chip surface area of a DRAM cell, particular challenges are presented. Narrower trench capacitors have smaller trench openings at the chip surface. Since the fabrication of a trench capacitor requires successive steps of deposition and etching of material layers through the trench opening, a narrow trench can become clogged, a condition commonly referred to as “pinchoff”. In pinchoff, the opening of the trench may close up entirely or otherwise leave insufficient space for the deposition and etching steps are performed inside the trench.
This problem is particularly exacerbated by the thickness of the collar. In fact, in processing trenches at an exemplary width today (90 nm), formation of the final isolation collar prior to formation of the trench capacitor is no longer possible. This is because the final collar typically has a thickness of 30 nm on each sidewall of the trench. Given that the collar is formed on both sidewalls of the trench, in a 90 nm wide etched opening, the collar would leave an opening of only 30 nm through which all subsequent processing would need to be performed.
More recent approaches are focused on use of a thinner, i.e. significantly thinner than 30 nm, sacrificial collar to protect the upper portion of the trench during processing to form the trench capacitor. After such processing, the sacrificial collar is removed and later replaced with the final isolation collar.
In the prior art, there are two main classes of methods of trench processing that utilize a sacrificial collar in the upper part of a deep trench. In the first class, the deep trench is formed by a one-step process, preferably by reactive ion etching (RIE). A sacrificial collar is formed after etching the deep trench. Three common processes in this class are briefly described as follows, along with their inherent limitations.
These three processes are the anti-collar scheme, the sacrificial polysilicon scheme and the modified anti-collar scheme. In the anti-collar scheme, an oxide layer is first formed on the sidewalls of the trench. The trench is then filled with resist, and the top surface of the resist is recessed to a predetermined depth below the top of the trench. Thereafter, the oxide is removed from the upper portion of the trench. Then, the resist in the lower portion of the trench is stripped. This leaves only the bottom portion of the trench sidewalls covered by oxide. Next, the wafer is exposed to a nitrogen-containing atmosphere, such as NH3. By this step, a thin layer of nitride is thermally grown on the trench sidewalls only in the upper portion of the trench. The oxide in the lower portion prevents the nitride from being grown there. Thereafter, the oxide is removed from the sidewalls in the lower portion of the trench, leaving the nitride collar in the upper portion only.
An inherent limitation of the anti-collar scheme is that the maximum thickness of nitride that can be grown thermally is limited to about 25 Å. A layer having such thickness is not sufficient to act as a collar for subsequent processing.
The second method, the sacrificial polysilicon scheme, begins with the formation of a first oxide layer on the trench sidewalls, typically by thermal oxidation. A first nitride layer is then formed on the trench sidewalls by low pressure chemical vapor deposition (LPCVD). The trench is thereafter filled with polysilicon, and the top surface of the polysilicon is recessed to a predetermined depth below the top of the trench. Using in-situ steam growth (ISSG), the polysilicon and nitride surfaces are oxidized, and then a second layer of nitride is deposited by LPCVD. Anisotropic etch by reactive ion etching (RIE) is then used to remove the nitride and ISSG oxide on the polysilicon, while leaving the nitride and ISSG oxide on the sidewalls of the trench. An aggressive etch follows, in order to remove all of the polysilicon in the trench bottom portion.
The first nitride layer in the lower trench portion is then stripped, stopping on the first oxide layer. Simultaneously, the second nitride layer in the upper trench portion is stripped. The first oxide layer in the lower trench portion and ISSG oxide on the upper trench portion are then stripped, leaving a collar formed in the upper trench portion only. The resulting collar includes a thin layer of oxide and a layer of nitride.
Unlike the anti-collar scheme in which the nitride collar is formed by thermal growth, the nitride in the sacrificial polysilicon scheme is formed by LPCVD. Therefore, the nitride in the sacrificial polysilicon scheme may be of any thickness. This scheme, however, suffers from the following disadvantages: process complexity, and severe defect generation during polysilicon removal from the lower trench portion. The removal process must be very aggressive in order to completely remove the polysilicon. This may cause severe defect issues such as pinholes on the trench sidewall and damage to some surface features of the substrate such as alignment marks.
In the third process, the modified anti-collar scheme, a first oxide layer is formed on the trench sidewalls by thermal growth. Thereafter, a first nitride layer is formed on the first oxide layer by LPCVD. Then, a second oxide layer is formed on the nitride layer. Thereafter, a thin layer of polysilicon is deposited on the second oxide layer, and then the surface of the polysilicon is oxidized to form a third oxide layer. In such manner, a stack of three oxide layers and one nitride layer are formed on the sidewalls of the trench. The trench is then filled with resist, and the top surface of the resist is recessed to a pre-determined depth below the top of the trench. The third oxide layer is then removed from the exposed top portion of the trench sidewall, and then the resist is stripped. A second nitride layer is formed on the upper trench portion only by thermal nitridation. The bottom portion of the trench is covered by the third oxide, thereby inhibiting nitride growth on the lower trench portion. The third oxide is then stripped from the trench bottom portion, using a removal process which is selective to the second nitride layer. The polysilicon is then stripped from the lower trench portion, using a removal process which is selective to the second nitride layer. The first nitride layer is then stripped from the lower trench portion, stopping on the first oxide layer. Simultaneously, the second nitride layer on the upper trench portion is stripped, stopping on the polysilicon layer. The polysilicon layer is then stripped from the upper trench portion. The first oxide layer is then stripped from the lower trench portion. Simultaneously, the second oxide layer on the upper trench portion is stripped. A collar is thereby formed on in the upper trench portion only. Similar to the sacrificial polysilicon scheme, the collar includes a thin layer of oxide and a layer of nitride.
An advantage of the modified anti-collar scheme is that it avoids the aggressive polysilicon removal step. However, its disadvantages include: process complexity, poor collar quality in which the sacrificial collar can have “pinholes” due to the conditions in which the thin films are deposited. The multiple layers of film deposition may cause a high defect density in the sacrificial nitride collar. This process is also subject to the possibility of pinch-off in narrow trenches.
U.S. Pat. No. 5,482,883 describes a process in which a trench is formed by a two-step etch. As described in that patent, a trench is etched to a predetermined depth. A collar is then formed on the trench sidewall, and then a second etch is performed to reach the final depth of the deep trench. A problem of that process is collar integrity. In that process, it appears difficult to form a collar having good integrity because the collar is exposed to and damaged by ions and plasma during the second etch.
Consequently, an improved method of trench fabrication is needed using a sacrificial collar structure that avoids the problems of the prior art methods currently being practiced. The present invention provides such an improved method.
In addition to the above-described challenges of fabricating trench capacitors, the structure of the deep trench itself poses challenges to the achievement of desirable DRAM cell. For the vertical transistor in the upper portion of the trench to have good performance, it would be desirable for the deep trench to have a rectangular shaped cross-section, when viewed from top down looking into the trench.
However, resolution limits make that goal difficult to achieve by photolithography. Trenches having minimum width, i.e. width at the minimum lithographic feature size F, for example 90 nm, cannot be patterned lithographically and etched by conventional methods to provide a rectangular shaped cross-section. Instead, resolution limits cause trenches at that feature size to be patterned and etched in a somewhat octagonal shape. The octagonal shape is undesirable because it presents a set of three angled trench sidewalls to the active area at the main surface of the semiconductor substrate. Variations in the electric field at vertices between the trench sidewalls decrease performance of a transistor formed vertically along those sidewalls.
In view of the foregoing, it would be desirable to provide a two-step deep trench etch process in which a sacrificial collar is formed after the first etch step. In such manner, the sacrificial collar desirably retains satisfactory integrity during and after the second deep etch step.
It would further be desirable, in a two-step deep trench etch process, to widen the upper portion of a trench after a first trench etch step, prior to forming a sacrificial collar on the upper portion of the trench.
It would further be desirable, in a two-step deep trench etch process, to widen the upper portion of the trench in a semiconductor substrate selectively to one or more overlying layers serving as a mask for the second deep etch step. In such manner, an overhang would be desirably disposed over the sidewalls of the upper portion of the trench. Moreover, a sacrificial collar formed in the upper portion is desirably protected by the overhang from damage during the second, deep etch step.
It may further be desirable, in a two-step deep trench etch process, to widen the upper portion of the trench in a semiconductor substrate in an anisotropic manner to reshape the trench to a rectangular form. In such manner, the trench desirably presents a single planar surface to an active area at a main surface of the semiconductor substrate.